Downscaling of MOS transistors and their use in CMOS circuits has driven semiconductor industry growth and has constantly improved integrated circuit (IC) characteristics. Although the number of transistors allowed on a single chip has increased while the price per logic function has decreased, MOS transistor dimensions are approaching physical limitations. The surrounding gate (SG) and double gate (DG) MOSFET structure offer the most promise for structures having sub-50nm channel lengths, since it can efficiently suppress short-channel effects, eliminate substrage effects, and minimize leakage currents. Although FinFET presents the most cost-effective method for implementing SG and DG MOSFET structure, all existing Fin FET structures suffer from several limitations, such as degraded channel mobility on the active sidewall surfaces, low current drivability per ship area, large parasitic series resistances, high-cost, and difficulty in integrating with bipolar process for BiCMOS circuits.
Scientists at the University of California have developed a novel high aspect ratio FinFET (HR FinFET) that overcomes these limitations, while also improving their characteristics. This invention enhances the capabilities of FinFET to extend conventional CMOS performance.
The new UC technology provides the following benefits: