In current vertical gate-depleted single electron transistors, the mesa must be etched to the point just below the tunneling barrier. In addition, the gate Schottky contact must wrap the pillar containing the tunneling barriers. These requirements considerably complicate the processing of these devices.
Scientists at the University of California have developed a novel approach to fabricating these devices which greatly simplifies the process while allowing the gate to be split into multiple gates.
ADVANTAGES: The new UC technology provides the following benefits:
|United States Of America||Issued Patent||7,547,932||06/16/2009||2002-421|