| Tech ID |
Title |
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| 23256 |
LACVD Thin Film Encapsulation of Organic Optoelectronic Devices
Organic electronic devices such as organic light emitting diode (OLED) and organic photovoltaics (OPV) must be protected from water and moisture, which can react with both organic and inorganic active layers and degrade performance. Thin film inorganic layers can be deposited by sputtering, but they tend to produce a large number of defects. The standard CVD requires high temperature and so is incompatible with OLED. Plasma enhanced CVD (PECVD) reduces processing temperature but suffers from heavy ion bombardment, and plasma-induced vacuum ultraviolet (VUV) irradiation onto the sample. To address these challenges, investigators at University of California at Berkeley have developed a laser-assisted chemical vapor deposition (LACVD) system for providing thin film oxide & nitride encapsulation of organic electronic devices. This LACVD encapsulation system allows, for the first time, encapsulation of organic optoelectronic devices, such as organic light emitting diodes (OLED) and organic photovoltaics (OPV). Low substrate temperature operation by LACVD permits deposition on temperature-sensitive materials such as polyacrylate layer.
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| | 23223 |
Layout Optimization for Time-dependent Dielectric Breakdown Reliability in VLSI
Time-dependent dielectric breakdown (TDDB) is becoming a critical reliability issue in VLSI design, since the electric field across dielectrics barriers increases as technology scales downward. Moreover, dielectric reliability is aggravated when interconnect spacings vary due to misalignment between via and wire masks. Although dielectric reliability can be mitigated by a larger interconnect pitch, such a guardband leads to significant area overhead.
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| | 23076 |
Improved Gallium Nitride (GaN) Thermoelectric Devices
A novel method of enhancing cross-plane thermoelectric properties, resulting in increased efficiency and a higher figure of merit (ZT).
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| | 23075 |
Enhancement Of Thermoelectric Properties Through Polarization Engineering
A novel method of enhancing the thermoelectric properties of materials used in thermoelectric power generation.
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| | 22863 |
Sub-volt Electro-optic Modulator with 100 GHz Bandwidth
An electro-optic modulator with 100 GHz bandwidth that requires less than 1V to turn on and off.
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| | 22774 |
Method Of Forming Flexible Thermoelectric Devices
Thermoelectric devices are made from rigid bulk or bulk like material which are inherently inflexible. Alternative thermoelectric device designs which incorporate semiconducting nanowires are able to be rigid and yet be flexible. For example, despite the rigidity of semiconducting nanowires they can move independently from each other, enabling flexible thermoelectric device designs. The use of rigid or semi-rigid electrodes for flexible thermoelectric devices causes many difficulties including but not limited to stiffening the device, creating stresses in the active material contacts, and fracturing the active material and contacts. Flexible metallic materials are essential in developing thermoelectric device as envisioned by UCSC researchers.
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| | 22773 |
Thermoelectric Devices With Spatially-Varying Fraction Of Active To Insulation Region
In many thermoelectric applications there is benefit in heterogeneously combining an active thermoelectric conversion material with a good thermal and electrical insulator including air or vacuum as possible candidates. In such configurations it is possible to decrease the cost of device fabrication due to decreased material costs. It is also possible to tune the total thermal resistance of a system by tuning the fraction of active to insulating (Atol) region which can in turn be used to select the operating temperature if the heat flux is known as is often the case. The ability to tune the temperature by controlling the fraction of Atol will enable designers to create devices which operate at optimal temperature ranges for decreased cost. Design challenges include overcoming electrical resistance resulting from strategic reduction in materials and the increased parasitic electrical and thermal resistances due to the avoidance of the heat-spreader with expected resistance to conduction.
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| | 22760 |
Wafer Scale Integration of CMOS Chips for Biomedical Applications
A novel technique for the integration of small complementary metal-oxide semiconductor (CMOS) chips into a large area substrate.
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| | 22636 |
Microfluidic-Ribbon Printer
High-throughput, automated, large-scale mircoarry format assay in a short time frame and at low cost.
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| | 22568 |
Ferromagnetic Material - Semiconductor Nano-Composite Spin Injector
Unlike conventional FETs that operate on electric current, spin FETs utilize the application of an electron's two spin states. In order to compose a spin FET, a ferromagnetic material is placed between two semiconductors. A key advantage of using spin FETs over traditional FETs is that the spin state of an electron can be detected and altered without necessarily requiring the application of current. Today, FETs are the fundamental building block for electronic devices however the spin FET may eventually provide a viable alternative to Si CMOS technologies. The paramount challenge to constructing spin FETs is the process of electronically injecting spin-polarized electrons or holes into the semiconductor channel region at room temperature. The electrical conductivity mismatch between ferromagnetic materials and semiconductors make efficient spin injection fundamentally prohibitive for diffusion based current injection. Another approach to constructing spin FETs is to use a tunnel injection method but this procedure creates a high contact resistance which is detrimental to FET operations. Thus, a more efficient spin injection approach is needed for the realization of efficient spin FETs.
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| | 22365 |
Low Carrier Loss Device Structure for High Performance Green LEDs
A novel light-emitting device structure that reduces the effects of these misfit dislocations by maintaining low carrier loss in the active region of the device.
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| | 22364 |
Current Aperture Vertical Electron Transistor (CAVET) for High Power Applications
A process for creating a novel type of active current-blocking layer to allow the device current to only pass through the aperture.
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| | 22295 |
LED Structure with Low Efficiency Droop for High-Current Applications
A novel LED structure that shows reduced droop effects when driven with high currents.
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| | 22230 |
Photolithography High Resolution Patterning
Photolithography, an essential process in the fabrication of integrated circuits, has undergone continuous advancements that allow patterning of nanometer sized features. For example, features as small as 50 nm can be made by using excimer lasers with wavelengths of 248 nm and 193 nm (i.e., deep ultraviolet light). However, it is not always feasible for scientists to use the short wavelength lasers because they are expensive. A method that allows for high resolution photolithography without large capital expenses will be very useful. Researchers at the University of California, Irvine have developed a photolithography method that allows for high resolution patterning. By using this method, one can get a 20-fold improvement in the limit of resolution in comparison to the inherent resolution of “top-down” processing. In addition, the method is easy to use, inexpensive, and does not require sophisticated instrumentation.
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| | 22016 |
MEMS Resonators with Increased Quality Factor
On-chip capacitively transduced vibrating polysilicon micromechanical resonators have achieved quality factor Q's over 160,000 at 61 MHz and larger than 14,000 at about 1.5 GHz -- making them suitable for on-chip frequency selecting and setting elements for filters and oscillators in wireless communication applications. However, there are applications -- such as software-defined cognitive radio, that require even higher Q's at RF to enable low-loss selection of single channels (instead of bands) to reduce power consumption down to levels conducive to battery-powered handheld devices. To address those higher Q RF applications, researchers at UC Berkeley have invented design improvements to MEMS resonators that reduce energy loss and in turn increase resonator Q. In reducing energy loss to the substrate while supporting all-polysilicon UHF MEMS disk resonators, the Berkeley design improvements enable quality factors as high as 56,061 at 329 MHz and 93,231 at 178 MHz -- that are values in the same range as previous disk resonators using multiple materials with more complex fabrication processes. Measurements confirm Q improvements of 2.6X for contour modes at 154 MHz, and 2.9X for wine glass modes around 112 MHz over values achieved by all-polysilicon resonators with identical dimensions. The results not only demonstrate an effective Q-enhancement method with minimal increase in fabrication complexity, but also provide insights into energy loss mechanisms that have been largely responsible for limiting Q's attainable by all-polysilicon capacitively transduced MEMS resonators.
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| | 22004 |
Micro Optical Waveguide Manufactured From Laminates
A cantilever waveguide fabricated from laminate materials and integrated onto a printed circuit board (PCB). New fabrication and packaging methods were also developed in creating an electro-optical sensor device.
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| | 22003 |
New Bootstrap Gate Drivers For Multilevel Converters
A new circuit and control method consisting of new bootstrap gate drivers with the redundant switching states for the multilevel converters. Based on the new bootstrap capacitor charging method and the use of the redundant switching states, the proposed bootstrap gate drivers can achieve stable bootstrap capacitor voltages with minimum capacitance and wide operation range.
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| | 21701 |
MEMS Tunable Capacitor Based On Angular Vertical Comb Drives
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| | 21695 |
Bottom Insulating Gate Vertical Organic Transistor
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| | 21690 |
Write-Once-Read-Many Plastic Memory
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| | 21259 |
Femtosecond Laser Pulse Compression With Variable Phase Plate
Mode-locked lasers are widely used to produce ultrashort light pulses (in the femtosecond range), for use in science and industry. Poor dispersion compensation, also called chirp, is a limiting factor in reducing the pulse length in many of these systems. While linear chirp can be eliminated with simple and mature technology—grating pairs, chirped mirrors, dispersion-compensating fibers, etc.—higher-order chirp is more difficult to eliminate. One approach to eliminating higher-order chirp is to use a programmable spatial light modulator—for example, a liquid-crystal or acousto-optic modulator—in the Fourier plane of a grating pair. These modulators, however, are very expensive, easily damaged, and absorb some of the light. Deformable mirrors can perform a similar role, but are also very expensive. Other approaches to tunably compensate higher-order chirp require extra optical components that make them difficult to align and adjust. Still other approaches are not tunable, or else tunable over only one degree of freedom. The present invention is an optical component that compensates higher-order chirp. It is very inexpensive and simple to manufacture, has low light loss, and has enormous damage threshold. Most importantly, it has three independent degrees of freedom, which adjust linear chirp, quadratic chirp, and cubic chirp. Each of these adjustments requires no realignment: Only the component itself needs to be adjusted. Therefore the invention could have widespread use, both as an OEM component of commercial lasers, and also as an easily-implemented upgrade to legacy systems.
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| | 21090 |
Low Noise, Stable Avalanche Photodiode
A new avalanche photodiode that is low noise and provides a highly stable gain at small bias voltages.
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| | 20588 |
Dry Adhesion and Patterning of Nanomaterials on Tacky Photopolymer
Using the Tacky Dot®, UC San Diego researchers have adapted the technology to the patterning of carbon nanotubes, nanowires, and other types of nano-materials. This technology places the nanomaterials on the surface of the photopolymer, sandwiched with other materials or in layers to form a structure of nanomaterial. The dry method removes both the need for the use of a flux, which is found in wet methods, and the need to anneal the surface to fix the nanomaterials in place. The method is capable of producing patterns whose size is just a few microns.
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| | 20567 |
Nanostructured Electron-Injection Materials and Electroluminescence Method and Device
Lighting is a major contributor to electricity consumption, accounting for 19 percent of global use and 34 percent in the U.S. The U.S. lighting market is currently dominated by the incandescent light bulb, which is only 5 percent efficient whereas the fluorescent lamp is 15 to 25 percent efficient. Solid-state luminaires, which are typically based on light-emitting diodes (LEDs), have the potential to revolutionize the industry with higher efficiency, better quality, and lower maintenance, possibly leading to a reduction of half the energy consumed by general illumination. For example, 30 percent efficiency has been achieved in a commercially available white LED and 50 percent in a laboratory white LED device. White light in such devices is produced either by combining light from different color LEDs or taking blue or near-UV light from an LED to “pump” a mixture of phosphors. The phosphor approach, when implemented with conventional phosphors, produces cold white light that is not color tunable and has non-optimal efficiency, but has the potential to overcome these shortcomings with the use of advances in materials.The appreciable energy savings derived by converting from incandescent to fluorescent lamps and solid-state lighting has spurred government measures towards phasing out incandescent light bulbs. The general lighting market is predicted to exceed $130 billion by 2011 with the LED-based share forecasted to grow to $1.4 billion by 2012. There is clearly an unmet need and great market opportunity for new energy-efficient lighting devices.
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| | 20539 |
Horizontal Current Bulk Bipolar Transistor
Current, state of the art bipolar transistors are processed with self-aligned, double polysilicon, trench-isolated layers, which have not changed the device geometry or the placement of electrodes and subsequently prevented the scaling and ultimately limited the minimum size of these devices.
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| | 20467 |
On-chip, Real-time Feedback Control For Electrical Manipulation Of Droplets
The uniformity of each droplets volume in a digital microfluidic system is useful and often critical to the overall functions. Digitization of liquids, e.g. generating droplets from liquid reservoirs, is a key step to determine the droplet volume. Reasonable level of accuracy can be achieved by simple signal switching during the digitizing processes. However, the performance is subject to random variations over the devices and operation conditions. The known feedback mechanisms to control droplet uniformity required external equipments (pumps and valves) in the system hardware and closed the loop once per droplet in the feedback algorithm (i.e., the feedback is droplet-to-droplet).
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| | 20264 |
Droplet Microfluidics On Multi-layer Printed Circuit Board
Microfluidic devices can be used to control the movement of minute amounts of liquids. Printed circuit board (PCB) technology with modified fabrication processes has been used to allow electric connections to any points on the surface independently. Such a surface, with independently accessible, direct-referencing electrodes, would require costly integrated-circuit (IC) fabrication methods, which are not well-suited to the high surface area of microfluidic systems.
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| | 20249 |
Submillimeter-wave Signal Generation By Linear Superimposition Of Phase-shifted Fundamental Tone Signals
Because of nonlinear effects, it is virtually impossible to generate useable submillimeter waves of a frequency greater than 190GHz using CMOS oscillators. In conventional oscillator circuits, which are nonlinear systems, increases in frequency are accompanied by a corresponding loss in gain or efficiency and an increase in noise.
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| | 20163 |
New Materials For The Formation Of Polymer Junction Diodes
Compared to conventional semiconductor devices, polymer semiconductor devices are particularly attractive for applications in which flexibility, light weight, large-area thin film, low-cost, and/or environmentally safe characteristics are important. However, despite these potential advantages, devices made from neutral conjugated polymers have found limited applications due to their low carrier mobility and charge injection barrier at the polymer/electrode interfaces. Polymer devices that could overcome these limitations and offer the advantages listed above would be of great benefit. The p-i-n junction diodes disclosed here do exactly that: they overcome the noted limitations while exhibiting many of the benefits associated with polymer devices.
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| | 20152 |
Micropumping of Liquids by Directional Growth and Selective Venting of Bubbles
Micropumps are a critical element of microfluidics, as they are required to move small volumes of liquid in a controlled, energy-efficient manner. Several categories of micropumps have been reported, such as mechanical micropumps, electrokinetic micropumps, and valveless bubble-driven micropumps. The valveless bubble pumps are attractive for microfluidics because of their simplicity in fabrication over mechanical pumps and their flexibility in working liquids over electrokinetic pumps. The preferred method to date of generating bubbles in the valveless pump is by thermal generation (boiling). However, this method has several limitations. First, boiling requires high levels of energy to induce vapor formation. Second, the vapor condenses back to liquids much slower than they boiled, which limits the cycling speed of the pumping action. Another common bubble generation methods for the valveless pump is electrolysis, but they are not suitable for closed systems, such as fuel cells, because of the inability to eliminate the gas bubbles.
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| | 20149 |
Electronic Devices With Carbon Nanotube Components
Flexible and transparent transistors have recently resulted in several noteworthy achievements. Transparent transistors have been fabricated using both polymers and inorganic oxides. Both have significant deficiencies, however. Polymers have low mobility and inorganic oxides do not have the desired flexibility and simplicity in manufacture. In current transistor configurations, the gate and also the source and drain are metal electrodes, and thus are neither flexible nor transparent. In addition there is usually a large interface resistance between the electrodes and the carbon nanotubes network. Furthermore, there is a need for a simple method of fabrication, where the different layers that form the transistors and the fabrication of the different layers are compatible.
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| | 20104 |
High Power, Ultra-fast Integrated Semiconductor Laser
This invention is a part of a research effort that will enable a quantam leap in the performance of high bit rate optical communication systems. The research products of this effort will include femtosecond semiconductor lasers with high pulse energy.Monolithic mode-locked semiconductor lasers generating sub-picosecond optical pulses with high pulse energy play an important role for electro-optic sampling and high bit rate TDM systems. Though such short optical pulses have been demonstrated in semiconductor gain medium using external cavities and additional pulse compression, those lasers are very bulky and not suitable for practical applications. Monolithic mode-locked semiconductor lasers are compact, light weight, energy efficient and do not require optical alignment. Although very impressive performance (600 fs pulse width, 350 GHz repitition frequency) has been demonstrated, the pulse energy of this type of multiple-contact quantum well lasers is limited by the intra-cavity saturable absorber (approx.10 fJ). Such energy is insufficient for most all-optical switching/demultiplexing systems.The subject invention is a new integration scheme for realizing novel femtosecond semiconductor lasers with an integrated antiresonant Fabry-Perot saturable absorber (A-FPSA). Such lasers have several unique advantages: (1) ultrashort pulse generation that fully exploits the gain bandwidth of semiconductor quantam wells; (2) high power operation (average power > 50mW) because the saturable absorber is placed inside the antiresonant FP cavity; (3) it enables intra-cavity dispersion compensation for the first time in monolithic cavities, which could further shorten the pulse width (the gain bandwidth of semiconductor could support pulses as short as 50 fs). These performances represent one to two orders of magnitudes improvement over the conventional monolithic mode-locked lasers. In this scheme, the saturable absorber is decoupled from the gain medium and, therefore, can be separately optimized for shorter pulses. For example, it can be made into fast saturable absorber by employing low-temperature grown GaAs. (2) By placing the saturable absorber layer inside an antiresonant Fabry-Perot cavity, its saturation energy can be increased by 100 times (1 to 10 pJ). Thus much higher peak/average power can be obtained from the proposed femtosecond semiconductor laser.
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| | 19229 |
High-Efficiency Dye-Sensitized Solar Cells Based on TiO2 Nanotubes
Photovoltaics have thus far been largely based on semiconductors, e.g., Si, CdTe, and cadmium indium selenide. Solar cells using these materials have increasingly been available commercially but still need improvement relative to stability, cost, and environmental concerns. A leading alternative solar-cell technology relies on photoelectrochemistry and the absorption and excited-state properties of dye molecules bound to a TiO2 substrate. Research on such dye-sensitized solar cells (DSSCs) has targeted and achieved higher efficiency. The prevailing approach in fabricating DSSCs has been based on mesoporous random networks of TiO2 nanocrystals. This approach however suffers from increases in resistance and recombination losses.
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| | 19228 |
Memory-Resistor Emulator
The invention provides an electronic circuit that realistically mimics the function of a memory resistor. The memory resistor emulator may be used alone or as a part of an electronic circuit. The memory resistor emulator includes several intrinsic features of a memory resistor. First, from the point of view of an external circuit, the memory resistor emulator behaves as a passive electronic device. Second, the response of the memory resistor emulator to the applied voltage can be selected very close to the response of a real memory resistor. Third, the frequency behavior of the memory resistor emulator (in a certain frequency range) can also be selected very close to the frequency dependence of the real memory resistor.
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| | 19226 |
6-18 GHz 8-Element SiGe Phased Array Beamformer Chip
This invention is a 6-18 GHz 8-element SiGe phased array beamformer chip, including GSDII layout files, design-files compatible with Jazz Semiconductor’s SBC18Hx process detailing circuit design, and the following supporting published literature: Kwang-Jin Koh; Rebeiz, G.M.; “An X- and Ku-Band 8-Element Phased-Array Receiver in 0.18um SiGe BiCMOS Technology” Solid-State Circuits, IEEE Journal of, Volume 43, Issue 6, June 2008 Page(s):1360 – 1371. Sample chips are available. Additional chips may be ordered as-is for manufacture by Jazz Semiconductor. Specifics of the proto-type phased-array chips are as follows: 8-element phased array receiver in a standard 0.18- um SiGe BiCMOS technology for 6-18 GHz applications. The array receiver adopts the All-RF architecture, where the phase shifting and power combining are done at the RF level. With the integration of all the digital control circuitry and ESD protection for all I/O pads, the receiver consumes a current of 100-200 mA from a 3.3 V supply voltage. The receiver shows 1.5-24.5 dB of power gain per channel from a 50 ohm load at 12 GHz with bias current control, and an associated NF of 4.2 dB (at maximum gain) to 13.2 dB (at minimum gain). The RMS gain error is < 0.9 dB and the RMS phase error is < 6 deg. at 6–18 GHz for all 4-bit phase states. The measured group delay is 162.5+/- 12.5 ps for all phase states at 6–18 GHz. The RMS phase mismatch and RMS gain mismatch among the eight channels are < 3 deg. and 0.4 dB, respectively, for all 16 phase states, over 6–18 GHz. The 8-element array can operate instantaneously at any center frequency and with a wide bandwidth (3 to 6 GHz, depending on the center frequency) given primarily by the 3 dB gain variation in the 6–18 GHz range. The chip size is 2.2 x 2.45 mm2 including all pads.
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| | 18961 |
Nanolasers For Ultra-High Density Heat Assisted Magnetic Recording
For the first time in the history of the multi-billion-dollar data storage industry, the conventional technology cannot be further scaled because of the fundamental limits of the materials. Specifically, superparamagnetism limits memory density in conventional technology. Heat assisted magnetic recording (HAMR) is believed to be one of the most promising alternative technologies developed in order to pack more memory into less space. The success of HAMR and other optical storage technologies depends on having a means to focus light in nanoscale spots with adequate intensity to record data. Currently, methods exist to focus lasers on small spot sizes, but these techniques do not deliver adequate power. Researchers at the University of California have developed a near field optical system capable of delivering light into a spot with a diameter of less than 30 nm and power values of above 100 nW. Furthermore, this technology is scalable down to a 5-nm diameter spot. The device is simple to manufacture using existing technology. The images above depict the UC nanolaser focused on an aluminum coated probe and the corresponding near-field intensity distribution of the spot. UC’s nanolaser could enable recording media with areal densities of greater than 10 terabits per square inch. With this technology the entire library of Congress could be carried in your wrist watch. The nanolaser could be used in various memory applications such as HAMR, protein based memory, and 3-dimensional multilevel recording. Additionally, the nanolaser could be used in future nanooptic or nanophotonics application such as optical interconnects to replace contacts and wires in future electronics, nanolasers for medical applications for ultra-precise diagnostics and surgery.
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| | 18654 |
Micromirrors With Precise Positioning
This micromirror is designed for precise positioning and eliminates the need for feedback control. Unlike comparable devices, this device does not suffer from typical alignment and sensitivity problems. Moreover, a fiber-optic crossbar switch with very low insertion loss can be constructed from this mechanism.
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| | 18411 |
Batch-processed Magnetic Microactuators
This batch-processed MEMS device features a large magnetically actuated force that is electrostatically addressed. It facilitates microstructures with high areal density and increased design flexibility. Also, its torsional flexure structure constrains motion to rotation about a single axis - which is ideal for various applications including micromirror systems as well as optical scanners, displays and switches.
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| | 18306 |
Fabrication Of Microstructures With High Vertical Aspect Ratios
Microscale structures are made by photolithography and etching of thin films, usually deposited by chemical vapor deposition. These processes limit the height of the structure to approximately the thickness of the deposited film. Chemical etching of silicon wafers produces milliscale structures, but these are restricted to certain crystal planes and cannot be used to make any shape that may be required. Researchers at the University of California, Berkeley have developed a method of fabricating milliscale structures (in excess of 150 microns) that may be fashioned into arbitrary shapes. The process developed at Berkeley may be used to produce microsensors such as accelerometers, microactuators such as valves to control fluidic circuits, and hollow thin film structures such as tubing manifolds and enclosed vessels for fluidic systems. Free-standing structures may also be fabricated.
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| | 18295 |
Silicon-on-insulator (soi) Transistors With Improved Current Characteristics And Reduced Electrostatic Discharge Susceptibility
Silicon-On-Insulator (SOI) technology has many advantages over its conventional bulk counterpart. However, SOI?s inherent floating body effect and high source/drain series resistance cause non-ideal behavior. Two new fabrication technologies developed by researchers at the University of California, Berkeley solve these SOI problems. The first technology is a low-barrier body-contact scheme that provides a substrate contact to the floating body for substrate current collection, thereby eliminating the floating-body effect. MOSFETs fabricated with this technology show bulk-like output resistance, high voltage gain, and low flicker noises. This design consumes a very small amount of area and is very effective in substrate current collection. The second technology is a recess channel MOSFET that consists of a thicker source/drain region and a thin channel, thereby resulting in a low source/drain series resistance without the use of a silicide. Furthermore, with this technique, ultra-thin film SOI MOSFETs can be fabricated without regard to the silicon consumption in the source/drain region when making contacts.
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| | 18294 |
Capacitorless, Silicon-on-insulator Dram Device
The great commercial success of DRAM can be attributed in large part to the continued miniaturization of the memory cell unit that in turn drives increased storage density and decreased costs. To further improve DRAM memory density, researchers at the University of California, Berkeley have developed a new technology that features a capacitorless DRAM (CDRAM) cell on Silicon-On-Insulator (SOI) substrate. The one transistor, capacitorless design of this innovative memory cell makes it very attractive for ultra high-density memory applications. To eliminate the need for a capacitor, the CDRAM device employs an operational concept similar to dynamic threshold. Previously proposed dynamic threshold cells, in which the charge is stored in a potential well formed by critically adjusting implantation, are sensitive to process conditions and are difficult to manufacture. In contrast, CDRAM, in which the charge is stored in the thin silicon film to modulate the threshold voltage, uses a simple fabrication process that exploits SOI technology. Furthermore, the amount of charge read in the CDRAM cell can easily exceed the amount of charge read in an ordinary DRAM cell (~100fC). Additionally, the CDRAM process is compatible with the general purpose SOI CMOS process and with the 10-mask, fully complementary SOI BiCMOS process?this makes CDRAM a solid candidate for future SOI VLSI applications.
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| | 18043 |
Air Corridor Interconnect Structure
In microchip structures the spaces between the metal elements in an interconnect structure are filled with solid dielectrics that typically have dielectric constants greater than two. This design approach, while somewhat effective, severally limits efforts at miniaturization of electronic components, an important motivator for current consumer products. In response to these challenges, researchers at the University of California, Berkeley have developed a novel structure and method of fabrication of metal elements which are supported by thin dielectric walls and open corridors which separate the walls from each other. Using this approach, the metal elements are effectively separated by the open corridors and not by a solid dielectric material. The corridors may be filled with a vacuum, or a partial vacuum, or a gas such as air, which typically have a dielectric constant of one. As a result, the parasitic capacitances between the metal elements can be reduced by about one-half, leading to improved circuit performance such as faster speed, lower cross-talk, and lower power consumption.
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| | 18024 |
Deep-subwavelength Photolithography
Photolithography is the most widely used micro-fabrication technique as it is a parallel, cost effective, and high throughput process. However, conventional photolithography techniques have a resolution limit that is about half of the illumination light wavelength in free space. To date, various approaches to improve photolithography resolution have developed, but each is flawed. For example, electron-beam lithography, focused ion-beam lithography and dip-pen lithography are slow series processes not suitable for large-area pattern fabrication, and implementing reduced wavelength illumination drastically increases instrument complexity and cost. To address these problems, Researchers at UC Berkeley have developed a family of deep-subwavelength photolithography technologies. These novel technologies are based on adding an artificial metal-dielectric structure to conventional photolithography processes to fabricate reduced patterns of the conventional photolithography masks. The technique overcomes the resolution limit of the conventional photolithography and can achieve deep-subwavelength resolution comparable to that of plasmonic nanolithography and near field contact photolithography. Furthermore, it can fabricate large-area uniform patterns while plasmonic nanolithography can not.
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| | 17893 |
High Efficiency Power Amplification Configuration For Portable Wireless Devices
Transmit power consumption often governs the ultimate battery lifetime of portable wireless communications devices, and therefore transmit power amplifiers used in these devises are important to their commercial success. The efficiencies of these power amplifiers are set by the capabilities of the semiconductor transistor devices that drive them. The most efficient power amplifier configurations operate their semiconductor transistors as switches that, if ideal, would not dissipate any power, making these amplifiers theoretically capable of achieving 100% drain efficiency. However, semiconductor transistor switches are not sufficiently ideal to allow these power amplifiers to achieve their efficiency potential. Instead, their finite series resistance, large input capacitance, nonlinear drain capacitance, substrate losses, voltage limitations, and temperature dependencies all contribute to lower effective efficiency. To achieve a more ideal efficiency for power amplification configurations, researchers at UC Berkeley have developed a switch design that reduces or eliminates many of the efficiencies of semiconductor transistor switches. In overcoming the long-standing impasse in power amplifier advancement, this innovative switch has the potential to open many new opportunities that include not only an increase in the talk-time of portable battery-powered wireless transceivers, but also a significant increase in the range of high power transmitters. The higher efficiency enabled by this Berkeley switch reduces the power dissipated in the amplifier itself, thereby lowering its temperature and allowing a further increase in output power -- that is further accommodated by the large voltage handling capability and better temperature resilience of the switch. The net result is a high power transmitter in a smaller and lower weight package.
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| | 17662 |
Zero-footprint Metrology Microsystem
In order to enable the reliable reproducibility of micro-scale devices used in high volume, low cost integrated circuit manufacturing, process parameters need to be directly measured and monitored during manufacturing. Probing optical beams that are directed from external photo sources have been used to probe in-situ information such as film thickness, material density, and refractive index. However in hostile processing situations that include plasmas, corrosive solutions, or polishing slurries, the environment interferes with these optical beams and consequently makes this approach infeasible. To address this problem, researchers at UC Berkeley have developed a new optical metrology microsystem that can be used in hostile environments. This microsystem can be implemented in a form-factor varying from a stand-alone mot-size device to a metrology wafer with an array of these metrology microsystems. To ensure accurate and precise measurements, an original implementation design and a dedicated data analysis algorithm have been developed that makes it possible to eliminate various implementation errors. The Berkeley researchers have successfully implemented this system in a prototype wafer with 3 x 3 metrology cells. Reflectance measurements showed that the system design and analysis algorithm works. Additionally, this prototype was calibrated using a SF6 plasma etching process of silicon oxide -- which further confirmed the validity of this design and methodology.
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| | 17657 |
MEMS Tunable Filters & Phase Shifters
Millimeter-wave systems can be used in many security and sensing applications including weather monitoring, vehicle crash avoidance, and aircraft landing guidance. These systems could significantly benefit from advanced tunable filters, especially for multi-channel communication systems. State-of-art tunable filters use solid-state varactors, but this design approach incurs high insertion loss, unacceptable signal-to-noise ratio, and rendered linearity. Tunable filters can also be designed using RF MEMS technology, however most of the existing designs of this type are discrete, lack the required resolution to continuously cover the desired operating band, and also suffer from high insertion loss. To address this problem, researchers at UC Berkeley have developed, demonstrated and characterized a new approach to designing W-band tunable filters. Prototypes of this Berkeley filter exhibited a 4.05 GHz bandwidth centered at 94.79 GHz with a minimum insertion loss of 2.37 dB, a return loss better than 15 dB, and a center frequency shift of 2.59 GHz. This novel type of tunable filter can also function in a dual role as a phase shifter. Prototypes achieved a phase shift of 110 degrees at 95 GHz.
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| | 17609 |
Nano-electro-mechanical Non-volatile Memory (nemory)
By the year 2018, MOSFET gate lengths for logic applications are expected to be scaled below l0nm with operating voltages below 1V. However, flash memory transistors are more difficult to scale because of the thick gate-stack equivalent oxide thickness (EOT) requirements for charge storage (threshold voltage shift) and retention. Although advanced transistor structures can be leveraged to improve gate-length scalability, high program/erase voltages are still required for fast operation. Thus, alternative integrated-circuit memory technologies such as magnetic RAM (MRAM) and phase-change memory (PCM) have been heavily investigated in recent years. These alternative memory technologies require new materials which increases process complexity and hence cost. In addition, their scalability to sub-10nm cell size is not assured. Therefore, there is a need for a new non-volatile memory technology that can be as scalable (in size and operating voltage) to match the scaling of logic devices. Researchers at UC Berkeley have developed a new design for nano-scale non-volatile memory. The design fabrication utilizes standard CMOS materials and processes. It leverages established surface micromachining technology and MEMS to achieve an elegantly simple and scalable memory cell structure that can potentially operate with very low voltage levels. The design is ideally suited for use in cross-point memory arrays for very high density non-volatile storage.
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| | 17535 |
Integration Of Advanced Structures With Conventional Integrated Circuits
Technological advances have allowed computer microprocessors to handle data at an extraordinary rate. However, the electrical interconnects within and between microprocessor chips introduce a severe bottle-neck to the flow of data. A promising architecture for next generation interconnects is high-speed and high-bandwidth optical interconnects, which will require heterogeneous integration of compound semiconductors with Si technologies. Some previously-explored methods for creating the optoelectronic circuitry include epitaxial growth, heteroepitaxial growth, and wafer-bonding. However, epitaxial growth of interconnections can produce large physical mismatches between desirable compound semiconductors and silicon; heteroepitaxial growth is complicated, expensive, and requires high processing temperatures that damage silicon-based circuitry; and wafer bonding is extremely susceptible to misalignments. Researchers at the University of California, Berkeley are developing advanced structures and methods for integration of compound semiconductors with conventional integrated circuit components to produce various active and passive optoelectronic components for optical interconnects, sensors, semiconductor lasers and other devices. The structures can accommodate quantum wells or quantum dots. The method under development at Berkeley will eliminate problems with alignment and processing temperature that constrain the application of conventional methods for fabricating optoelectronic circuitry.
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| | 17465 |
Optimized Mems And Microelectronics Design Using Evolutionary Multi-objective Optimization With Interactive Evolutionary Computation
Microelectrical mechanical systems (MEMS) are finding applications in a growing variety of fields that in aggregate are emerging as a large MEMS industry. However, despite the huge economic potential of MEMS, the current computer-aided design (CAD) tools for developing these complex devices are rudimentary. To address this situation, researchers at UC Berkeley have developed a MEMS CAD tool that combines evolutionary multi-objective optimization (EMO) with interactive evolutionary computation (IEC). The resulting hybrid solution enables complex MEMS to be designed with target specifications that are optimized for design constraints and competing performance goals. While other MEMS tools that use IEC have been developed, those tools are focused on mask layout, as well as fabrication and parametric modeling. In contrast, the Berkeley hybrid tool is focused on design synthesis. Furthermore, other CAD tools that use EMO depend on simulation software to evaluate design quality -- but many MEMS design issues can't be currently modeled and detected using simulations. However, these design issues can be readily identified by human visual inspection. By taking advantage of this human ability to perceive design flaws that can't be identified by software, this combined IEC - EMO approach produces superior designs with fewer manufacturing problems.
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| | 17405 |
Simplified Oscillator Circuit Design For Resonators
The layout of electrodes in the design of modern MEMS resonators has been one of the crucial aspects in ensuring a small feed-through capacitance. Consequently, complicated design are neccessary that usually require vacuum packaging to make sure that the parasitic feed-through capacitance does not render the resonator unusable. This vacuum must be maintained for the lifetime of the resonator. Approaches used to ensure correct resonator operation include: reduction of the minimum gap in the MEMS mechanical structure; the addition of CMOS transistors on the same substrate as the MEMS mechanical structure also known as integration with electronics; and vacuum encapsulation of the MEMS during the resonator fabrication instead of package level vacuum packaging. To address this complexity, researchers at the University of California, Berkeley have developed a simpler oscillator circuit that eliminates the effects of parasitic feed-through capacitance on resonators. This new circuit allows the operation of resonators with values of feed-through capacitance much larger than previously possible. As a result the new design enables simplification of the overall oscillator and resonator design and allows more freedom in the resonator architecture. The packaging of the MEMS resonator is simplified thereby reducing cost and increasing reliability. Vacuum packaging is no longer needed and minimization of feed-through capacitance can be less stringent with the new oscillator design. The new oscillator circuit supports MEMS fabrication processes with large gaps, and no integrated electronics or vacuum packaging (chip or package level).
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| | 17369 |
Low Cost Methods For Forming Hollow Out-of-plane Microneedles
There is growing interest in using arrays of hollow microneedles to implement minimally invasive, low-cost, highly integrated systems for delivering drugs to, or sampling fluids from humans. However most existing methods for fabricating microneedles are cost prohibitive and/or have design limitations. For example, existing fabrication concepts for hollow in-plane microneedles can only arrange the needles in one dimension which puts constraints on their flow capacity and rate. Likewise, lower costs methods using electroplated metals result in microneedle arrays that are not rigid enough for most applications. To solve this problem, researchers at the University of California, Berkeley have developed several low-cost methods for fabricating arrays of hollow, out-of-plane microneedles. These methods are based on using materials that are initially in fluid form such as curable polymers, polymer solutions or melts. The methods can be controlled to create microneedles with different geometries.
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| | 17358 |
Internal Electrostatic Transduction Resonators
Multiple resonators with different frequencies are essential in the design of micromechanical filters, oscillators and mixers. Lateral-mode resonators with a variety of resonant frequencies can be fabricated in the same lithography step using surface micromachining technology. However, these lateral-mode resonators have inefficient air-gap capacitive transducers that cause high motional impedance. To address this problem, researchers at the University of California, Berkeley have developed an electrostatic transducer for lateral-mode resonators in which the electrode gaps are filled with a dielectric material that has much higher permittivity than air. Previous dielectric transduction mechanisms rely on Poisson coupling between the SiN and silicon. However, this internal electrostatic transducer is directly coupled to the bulk acoustic mode of the lateral silicon resonator. As a result, the Berkeley design enables more efficient coupling between the transducer and resonator, and offers the potential to make an FBAR device entirely out of TiO2 instead of AiN. This internal electrostatic transducer has several advantages over both air-gap electrostatic and piezoelectric transduction including: lower motional impedance, compatibility with advanced scaled CMOS device technology, and extended dynamic range. Moreover, energy losses are minimized in the Berkeley transducer by matching the acoustic velocity of the dielectric material to the acoustic velocity of the resonator material.
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| | 17323 |
Method Of Selective Synthesis Of Nanomaterials
The unique electrical, mechanical and optical properties of nanowires and nanotubes makes them attractive in a variety of applications. However, a significant obstacle to the application of these nanostructures is the difficulty in handling, maneuvering and integrating them with microelectronics to form a complete system. In particular, current synthesis processes for silicon nanowires and carbon nanotubes require high temperatures that can damage the microelectronics on which the nanostructures are being synthesized. To solve these problems, researchers at the University of California, Berkeley have developed a process for synthesizing nanostructures at a specified location inside a room-temperature chamber. This localized selective synthesis process can directly integrate either silicon nanowires or carbon nanotubes with larger-scale systems, such as foundry-based microelectronics, and it eliminates the need for subsequent assembly processes. This innovative approach is based on localized resistive heating of suspended microstructures to activate vapor-deposition synthesis, and it yields either silicon nanowires or carbon nanotubes. The process has synthesized nanowires that grow at 1 ?m/min, are 30-80 nm in diameter, and up to 10 ?m in length; and the process has synthesized nanotubes that grow at 0.25 ?m/min, are 10-50 nm in diameter and up to 5 ?m in length.
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| | 17319 |
Platform For Batch Integration Of Dissociated Or Incompatible Technologies
The integration of various CMOS-based technologies and structures on a single, batch-processed wafer has great commercial potential. However these technologies and structures frequently have incompatible material as well as thermal or wafer-size fabrication characteristics that lead to application constraints, performance trade-offs and higher costs. To address these problems, researchers at the University of California, Berkeley have developed a fabrication technique that efficiently merges incompatible technologies, processes or structures on a common wafer platform resulting in a high level of integration with low parasitics. In comparison to other assembly techniques such as printed circuit boards, wire-bonding, flip-chip and interlaced processes, this Berkeley method is superior in that it: - Broadens the number of dissociated technologies that can be modularly integrated; - Minimizes parasitics through the use of integrated interconnects; - Offers higher throughput based on the batch process approach; - Saves on substrate area usage due to stacked high density integration; - Enables each modular fabrication to be dissociated and run in parallel.
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| | 17298 |
Vertical Comb Drive Torsional Microactuators And Fabrication Process Based On Self-aligned Plastic Deformation
Electrostatic comb-drives are used to make torsional actuators in numerous MEMS applications. However, the linkage- and hinge-designs of these actuators have reliability problems and limit maximum operation frequencies. Furthermore, existing designs are difficult to fabricate because the comb structures are challenging to align, or require elaborate wafer bonding, grinding, polishing and silicon anisotropic-etching processes. To improve the performance and simplify the fabrication of torsion-bar microactuators, researchers at UC Berkeley have developed torsional actuators that are made using self-aligned plastic deformation in a batch process. The microactuators are formed in simple, rugged single-crystal silicon and driven by vertical comb drives. The batch process is controllable, repeatable and does not include any critical alignment steps. Using this design, MEMS scanning mirrors have been built that resonate at frequencies between 1.90 and 5.33KHz achieving scanning angles up to 19.2 degrees with driving voltages of 40Vdc plus 13Vac. After more that 5 billion cycles of continuous testing at the maximum scanning angle, the plastically deformed silicon torsion bars have not exhibited any degradation or fatigue.
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| | 17253 |
Electrostatic Microactuator For Phase Micromirror Arrays
Micromirror arrays represent a huge market opportunity in a variety of sectors from optical displays, scanners and communication switches, to maskless lithography and optical spectroscopy. In the conventional design of these arrays, mirrors are mounted on tiltable cantilevers. However, in high frequency and analog applications a phased-mirror approach would be more useful. In this design, mirrors are shifted perpendicular to plane of the array to produce an image by interference effects. Unfortunately, no practical solution has been proposed to fabricate an electrostatically actuated dense array of phase micromirrors of micrometer size. To address this problem, researchers at the University of California at Berkeley have developed a MEMS-based microactuator for phase micromirror arrays. This electrostatic microactuator supports a rigid micromirror that is compliant only in the vertical direction. The fundamental advantage of this Berkeley microactator is that it can be manufactured by conventional MEMS fabrication techniques using standard semiconductor patterning and thin-film deposition processes. This low voltage actuator is conducive to fabricating flat and dense mirror arrays -- which is highly desirable in optical systems. Moreover, the device limits the range of actuation to prevent snap-down, and also provides damping to suppress mirror vibration.
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| | 17086 |
Method For Constructing Structures Using Nanoparticles
Using nanoparticles to construct microstructures on silicon chips is emerging as an important technique because of the comparatively low melting point of the nanoparticles. However, current construction methods require the presence of suitable substrate surface recesses that consequently hinder fabrication flexibility. To eliminate the need for substrate recesses, researchers at the UC Berkeley have developed a new process for constructing microstructures with nanoparticles. This method utilizes a laser light to partially melt nanoparticles, and upon solidification, the molten particles are sintered together to form the desired structure. Due to the low melting point of nanoparticles compared to that of bulk materials, this procedure avoids damage to the substrate and provides superior control over the structure construction process. This innovative technology can be used with a variety of delicate substrate materials in a normal atmospheric environment yielding a user friendly, fast, and cost effective process. This method has a wide array of metallic and non-metallic applications including formation of interconnections, MEMS, and superconductors.
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