Low Voltage Transistors

Background

A critical issue for scaled logic devices is the ability to operate with reduced power supply voltages, both in order to reduce power dissipation and in order to mitigate high electric field related problems. The sub-threshold swing of present metal oxide semiconductor (MOS) devices (at best 60 mV/decade), and the resultant leakage current, is a major impediment to further scaling of power supply voltage.

Technology Description

Engineers from UC San Diego have patented novel transistor designs having a substrate, a structure supported by the substrate including a source, drain, gate, and channel, wherein the source and the channel are made of different materials, and a tunnel junction formed between the source and the channel, whereby the tunnel junction is configured for injecting carriers from the source to the channel. The materials used in the source and the channel are different, and are chosen in order to optimize the tunneling current.

Advantages

 These new transistors are also able to turn on and off with only a small input voltage. In particular, the invention provides field effect transistors that achieve subthreshold swing lower than 60 mV/decade (which is the typical limit for conventional transistors). At the same time, transistors of the invention are capable of operation at high speeds.

Intellectual Property Info

This technology is protected by US Patent No. 8,148,718 and commercialization rights are available for license.

Patent Status