Methods For Integrated Circuit C4 Ball Placement Considering Package Reliability
Tech ID: 21670 / UC Case 2011-244-0
The magnitude of the I/O requirements for modern integrated circuits (ICs) continues to increase due to the growing complexity and size of ICs. The large I/O count found on most ICs has forced most designers to use flip-chip packaging instead of wire bonded packaging. Unfortunately, the solder bumps in flip-chip packages are susceptible to failure mechanisms such as thermal cycling and electromigration, especially in the presence of high temperatures. Thermal cycling failure is due to the Coefficient of Thermal Expansion (CTE) mismatch between the different layers in the package (substrate, underfill/C4 balls, and silicon die). C4 Balls experience large stresses caused by the different rates of thermal expansion between layers which, over many thermal cycles, can lead to crack formation and subsequent failure. Electromigration failure is due to the large current densities of the C4 power balls. Large temperature and temperature gradients, a common feature on most modern ICs, exacerbates the failure rate of both these processes. The researches at UCSC have developed two methods for combating C4 failure during the design stages of ICs, specifically at the CAD level.
UC Santa Cruz researchers have developed an algorithm which increases life-span of integrated circuits (IC’s) by optimizing reliability floorplanning on C4 balls used in flip-chip packaging. C4 ball (solder balls) life expectancy is improved 49 times on average as compared to HPWL (half perimeter wire length) optimization, by using UCSC quadratic pin placement algorithm. Algorithm targets placement of data I/O C4 balls to reduce failure rate from thermal-cycle fatigue by minimizing wirelength and increasing the number of cycles to failure.
I/O, IC, flip-chip, solder bumps, electromigration, thermal, expansion, C4, balls, temperature, floorplanning, algorithm,