Researchers at UCLA have developed a fault-tolerant logic resynthesis algorithm for LUT-based FPGAs which decreases the circuit fault rate without changing the topology of the logic network, thus eliminating the additional rounds of physical design that are required in conventional resynthesis algorithms.

Due to their design versatility and lower cost, FPGA systems are increasingly favored in comparison to their ASIC counterpart. However, because FPGA is more vulnerable to soft errors it is essential to improve its fault tolerance. While many techniques have been proposed, the majority do not preserve the topology of the logic network and therefore require a new round of physical design. This is not only costly and time-consuming, but it also delays convergence between logic and physical syntheses.

Researchers at UCLA have developed a low-cost technique to increase the fault-tolerance of LUT-based FPGA systems while preserving the function and the topology of the logic networks. Through implementing an in-place logic resynthesis algorithm, faults have less possibility of propagation and the overall system reliability is optimized. Furthermore, since the topology is preserved, the resynthesis algorithm can be applied post-layout and without requiring changes to the physical design, leading to a faster design closure.

LUT-based FPGA

• Internet routers, Telecommunication, Networking, Automotive and Consumer Application

Categorized As

• Semiconductors
  • Design and Fabrication
• Engineering
  • Other

Related cases

2010-140-0

Keywords

FPGA (Field Programmable Gate Array), LUT (Look Up Table), logic resynthesis, logic masking, fault tolerant, interconnect defect, configuration bit, soft error