High Aspect Ratio FinFET

Tech ID: 20295 / UC Case 2004-048-0

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Summary

UCLA researchers in the Department of Electrical Engineering have invented and reduced to practice a high aspect ratio field effect transistor. This manufacturing process circumvents key issues in the use of FinFET to implement surrounding gate and double gate MOSFETs.

Background

The reduced scale of CMOS technology to below 50 nm creates major problems of leakage current, short channel effects and gate dielectric tunneling. New structures are needed to circumvent these problems. Surrounding gate (SG) and double gate (DG) MOSFET is a promising structure for sub 50 nm channel lengths. The most cost effective way to implement SG and DG MOSFET is FinFET as described by Hisamoto et. al. in IEEE Transactions on Electronic Devices, December 2000. However, FinFET itself has problems. First is degraded channel mobility which reduces drain current and thus switching speed. There other issues of low current drivability, series parasitics, difficulty of BiCMOS integration and cost due to the difficulty of producing uniform size fins.

Innovation

A new FinFET structure is developed using (110) bulk silicon substrate and (111) sidewalls as the active device regions (fins). The fin is formed by using photo resist as a mask or by spacer masking. The invention describes the spacer masking approach. The spacer mask is aligned to the (111) crystal plane, which is perpendicular to the (110) bulk substrate. These are followed by ion implantation, nitride deposition and anisotropic etching, oxide selective removal, crystallographic dependant etching, gate oxidation, polysilicon deposition and finally CMP. Since wet crystallographic dependent etching is used, the fin sidewalls are free of defects caused by RIE. The result is a high aspect ratio in a smooth, planar surface, without metallization problems. The active portion of the fin can be made higher than 500 nm, compared to the current state of the art of 50 nm. This results in drive current increase by a factor of 10.The innovation lies the unique combination of bulk silicon processing steps. High aspect ratio FinFET can extend the performance of any CMOS application, particular for high performance switching. Due to the double gate principle of FinFET and its immunity to short channel effects, it is attractive for high frequency analog circuits, also called RF CMOS.

Applications

  • Analog, digital, and mixed-signal technologies;
  • High-speed microprocessors and high packing density memories;
  • Portable electronics that require low leakage currents;
  • High-frequency analog circuits (RF CMOS).

Inventors

  • Wang, Kang L.

Contact

Ben Chu / bchu@research.ucla.edu / tel: View Phone Number. Please reference Tech ID #20295.

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Categorized As

Related cases

2004-048-0

Keywords

semiconductor fabrication

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