UNIVERSITY of CALIFORNIA, SANTA BARBARA

Brief Description

A new and simple way to realize silicon-on-insulator (SOI) wafers with localized insulator region.

Background

Within the silicon-on-insulator (SOI) wafers the substrates are limited by thickness of the top device layer and BOX layer, plus potential surface morphology issue and material defects  

Description

Researchers at the University of California, Santa Barbara have developed a new and simple way to realize silicon-on-insulator (SOI) wafers with localized insulator region. The fabrication is implemented by well-known CMOS technology and completely compatible to current SOI wafer manufacturing flow.  

Advantages

• 4.5X lower thermal impedance
• Improved thermal dissipation capacity of electronic and photonic devices
• Higher output power and reduced threshold currents
• Different devices can be integrated on the same substrate easily

Applications

• Electronic and photonic devices    

 

This technology is available for licensing.

INVENTORS

• Liang, Di

Other Information

Contact

Franco Caporale/ caporale@tia.ucsb.edu / tel: 805-893-2073. Please reference Tech ID #18966.