A Highly Scalable DRAM Cell
Tech ID: 18948 / UC Case 2009-121-1
Brief Description
The concept of a capacitor-less DRAM cell was proposed to overcome scaling challenges for conventional 1-transistor/1-capacitor DRAM cells. The silicon-on-insulator (SOI) floating body cell (FBC) is a very compact capacitorless DRAM cell design, but it requires more expensive SOI substrates and is difficult to scale to very short channel lengths. The double-gate DRAM (DG-DRAM) cell was proposed as a more scalable design, and was recently demonstrated at 70nm gate length; however, it still has a relatively large cell size (8F2), is susceptible to disturbance within a memory array, and is not easily integrated into a conventional memory process flow.
To overcome these challenges, researchers at UC Berkeley have developed a new 4F2 double-gate vertical channel (DGVC) design that can be fabricated on a bulk-Si wafer using a conventional process flow. Retention and disturbance immunity characteristics of a DGVC cell are expected to be adequate for stand-alone memory applications, at the 22nm technology node (0.00194 ìm2 cell size). The design allows for longer channel lengths as compared to a planar channel design, so it is promising for 4F2 DRAM scaling to sub-22nm technology nodes.
Suggested uses
- DRAM Memory
Advantages
- Conventional process flow
- Stand-alone memory applications
Patent Status
Patent Pending
Inventors
- King Liu, Tsu Jae K.
- Kwon, Wookhyun
Other Information
Categorized As
Related cases
2009-121-1
Keywords
DRAM Memory
Contact
Curt Theisen / curt@berkeley.edu / tel: View Phone Number. Please reference Tech ID #18948.
